OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] - Rev 855

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
797 testsuite: kill test processes that timeout pgavin 4384d 05h /openrisc/trunk/or1ksim/
793 Corrected Julius Baxter's email address in MAINTAINERS jeremybennett 4404d 08h /openrisc/trunk/or1ksim/
792 Added a MAINTAINERS file.

012-04-07 Jeremy Bennett <jeremy.bennett@embecosm.com>

* MAINTAINERS: Added.
* configure: Regenerated.
* configure.ac: Updated version.
jeremybennett 4404d 08h /openrisc/trunk/or1ksim/
787 Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:

2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version.
jeremybennett 4419d 07h /openrisc/trunk/or1ksim/
784 Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.

2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour.
jeremybennett 4420d 22h /openrisc/trunk/or1ksim/
673 Multiple 64-bit fixes (mostly sign and size of constants). Fix bug #1. yannv 4517d 03h /openrisc/trunk/or1ksim/
625 Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. jeremybennett 4640d 05h /openrisc/trunk/or1ksim/
569 Added AM_SILENT_RULES for nicer builds olof 4678d 02h /openrisc/trunk/or1ksim/
566 or1ksim/eth: Fix ethernet file I/O on 64-bit machines stekern 4693d 22h /openrisc/trunk/or1ksim/
561 or1ksim - timer module, spr-defs.h re-bugfix julius 4704d 04h /openrisc/trunk/or1ksim/
559 or1ksim - spr-def.sh fix for timer julius 4705d 16h /openrisc/trunk/or1ksim/
556 or1ksim - added performance counters unit and test for it. julius 4709d 22h /openrisc/trunk/or1ksim/
552 or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets julius 4711d 06h /openrisc/trunk/or1ksim/
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 4738d 02h /openrisc/trunk/or1ksim/
532 Ensure the halted flag is cleared when the processor is unstalled. jeremybennett 4748d 23h /openrisc/trunk/or1ksim/
510 Updates for release 0.5.1rc1. jeremybennett 4769d 06h /openrisc/trunk/or1ksim/
508 Updates for Or1ksim 0.5.0rc3. jeremybennett 4770d 06h /openrisc/trunk/or1ksim/
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 4811d 23h /openrisc/trunk/or1ksim/
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 4835d 08h /openrisc/trunk/or1ksim/
472 Various changes which improve the quality of the tracing. jeremybennett 4854d 09h /openrisc/trunk/or1ksim/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.