OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [ChangeLog] - Rev 632

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
625 Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. jeremybennett 4662d 03h /openrisc/trunk/or1ksim/ChangeLog
561 or1ksim - timer module, spr-defs.h re-bugfix julius 4726d 02h /openrisc/trunk/or1ksim/ChangeLog
556 or1ksim - added performance counters unit and test for it. julius 4731d 19h /openrisc/trunk/or1ksim/ChangeLog
552 or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets julius 4733d 04h /openrisc/trunk/or1ksim/ChangeLog
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 4760d 00h /openrisc/trunk/or1ksim/ChangeLog
532 Ensure the halted flag is cleared when the processor is unstalled. jeremybennett 4770d 20h /openrisc/trunk/or1ksim/ChangeLog
510 Updates for release 0.5.1rc1. jeremybennett 4791d 04h /openrisc/trunk/or1ksim/ChangeLog
508 Updates for Or1ksim 0.5.0rc3. jeremybennett 4792d 03h /openrisc/trunk/or1ksim/ChangeLog
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 4833d 21h /openrisc/trunk/or1ksim/ChangeLog
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 4857d 05h /openrisc/trunk/or1ksim/ChangeLog
472 Various changes which improve the quality of the tracing. jeremybennett 4876d 06h /openrisc/trunk/or1ksim/ChangeLog
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4884d 04h /openrisc/trunk/or1ksim/ChangeLog
458 or1ksim testsuite updates julius 4885d 09h /openrisc/trunk/or1ksim/ChangeLog
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4893d 23h /openrisc/trunk/or1ksim/ChangeLog
451 More tidying up. jeremybennett 4904d 19h /openrisc/trunk/or1ksim/ChangeLog
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4904d 23h /openrisc/trunk/or1ksim/ChangeLog
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4910d 17h /openrisc/trunk/or1ksim/ChangeLog
440 Updated documentation to describe new Ethernet usage. jeremybennett 4911d 19h /openrisc/trunk/or1ksim/ChangeLog
437 Or1ksim - ethernet peripheral update, working much better. julius 4919d 14h /openrisc/trunk/or1ksim/ChangeLog
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4920d 14h /openrisc/trunk/or1ksim/ChangeLog

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.