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866 orpsocv2: correct build/par issue on Atlys board

From patch submission e-mail:

The first of the series is an issue that has been around since the
beginning (at least based on the svn log files) and traces its root to the
first Xilinx board supported by orpsocv2, the ML501. Apparently Makefile
for the final place-and-route process in all the builds contains a typo
which leads to the routing tool not using any timing constraint at all.

Patch by: Jason Zheng <jxzheng@gmail.com>
stekern 3886d 01h /openrisc/trunk/orpsocv2/
864 ORPSoC: Merge display_arch_state tasks

or1200-monitor contains the tasks display_arch_state and display_arch_state_except which are almost identical. This patch merges these two tasks into one, with a parameter to specify whether it should print out "(exception)" or not

Signed-off-by: Olof Kindgren <olof@opencores.org>
olof 4162d 07h /openrisc/trunk/orpsocv2/
863 ORPSoC: Add paramers to or1200-monitor for setting name and path of log files

Two small patches in one to make or1200-monitor more useful outside of orpsocv2:
- Setting log path with a parameter allows more flexible directory layout
- if the plusarg "testcase" is set at runtime, this is used to set a unique
prefix for the log files. Plusargs are currently not used in orpsocv2, so if
it is not set, the name falls back to the value of the parameter
TEST_NAME_STRING. The value of the parameter is set to the define
`TEST_NAME_STRING in the test bench top levele to avoid any changes to the
orpsocv2 scripts. With this, we can get rid of `include test-defines in
or1200_monitor.v

Signed-off-by: Olof Kindgren <olof@opencores.org>
olof 4168d 11h /openrisc/trunk/orpsocv2/
862 sysc: avoid using orpsoc internal classes directly

The problem with using the internal classes directly is
that you have to use the internally generated name,
this in itself is perhaps not such a big issue, the issue
is that the internal name changes when the underlaying verilog
design changes.
This works around this by using the classes through the
top module, which is part of the external api.
stekern 4179d 03h /openrisc/trunk/orpsocv2/
861 sysc: include unistd.h

write, read, pipe et al are declared in this, newer gcc will
warn on missing declerations, thus making the build to fail
stekern 4179d 03h /openrisc/trunk/orpsocv2/
860 or1200_monitor.v: Remove trailing whitespace olof 4183d 09h /openrisc/trunk/orpsocv2/
858 orpsoc/tests: Fix or1200-dsxinsn when caches are not present

This test would go into an endless loop when caches are not present.
stekern 4283d 16h /openrisc/trunk/orpsocv2/
857 orpsocv2: remove reference to r32 in context save/restore julius 4293d 06h /openrisc/trunk/orpsocv2/
854 Add OR1200_OR32_LWS define to board specific or1200_defines.v stekern 4390d 02h /openrisc/trunk/orpsocv2/
853 Declare pcreg_boot before usage

When things were moved around in rev 813, this error was introduced

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>
olof 4415d 11h /openrisc/trunk/orpsocv2/
850 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>
stekern 4430d 03h /openrisc/trunk/orpsocv2/
849 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>
stekern 4430d 03h /openrisc/trunk/orpsocv2/
848 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>
stekern 4430d 03h /openrisc/trunk/orpsocv2/
815 OR1200 debug unit: prevent deadlock when trap instruction stalls

As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.

The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result.
yannv 4450d 20h /openrisc/trunk/orpsocv2/
814 orpsoc/or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
olof 4465d 13h /openrisc/trunk/orpsocv2/
807 ORPSoC: Commit for bug 85 - add DSX support to OR1200.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85

Also added software tests, and added these tests to default regression test list
julius 4581d 07h /openrisc/trunk/orpsocv2/
805 ORPSoC: Fix for bug 90 - EPCR on range exception bug

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90
julius 4581d 07h /openrisc/trunk/orpsocv2/
803 ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91
julius 4581d 07h /openrisc/trunk/orpsocv2/
801 ORPSoC: Fix bug 88

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88
julius 4586d 12h /openrisc/trunk/orpsocv2/
794 ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file

Fixes lint warnings.
julius 4619d 22h /openrisc/trunk/orpsocv2/

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