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[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 408

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408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4937d 10h /openrisc/trunk/orpsocv2/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4938d 15h /openrisc/trunk/orpsocv2/
398 ORPSoCv2 removing generic backend path - not needed julius 4939d 22h /openrisc/trunk/orpsocv2/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4940d 21h /openrisc/trunk/orpsocv2/
396 ORPSoCv2 final software fixes...for now. See updated README julius 4943d 19h /openrisc/trunk/orpsocv2/
395 ORPSoCv2 moving ethernet tests to correct place julius 4943d 20h /openrisc/trunk/orpsocv2/
394 ORPSoCv2 removing unused directories julius 4943d 20h /openrisc/trunk/orpsocv2/
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 4943d 20h /openrisc/trunk/orpsocv2/
392 ORPSoCv2 software path reorganisation stage 1. julius 4944d 12h /openrisc/trunk/orpsocv2/
391 Removing modules no longer needed in ORPSoCv2 julius 4945d 13h /openrisc/trunk/orpsocv2/
374 ORPSoCv2 adding some files forgotten from last checkin julius 4976d 19h /openrisc/trunk/orpsocv2/
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 4976d 19h /openrisc/trunk/orpsocv2/
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 4988d 17h /openrisc/trunk/orpsocv2/
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 4989d 03h /openrisc/trunk/orpsocv2/
362 ORPSoCv2 verilator building working again. Board build fixes to follow julius 4990d 12h /openrisc/trunk/orpsocv2/
361 OPRSoCv2 - adding things left out in last check-in julius 4990d 16h /openrisc/trunk/orpsocv2/
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 4990d 17h /openrisc/trunk/orpsocv2/
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 4991d 02h /openrisc/trunk/orpsocv2/
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 4991d 11h /openrisc/trunk/orpsocv2/
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 4992d 17h /openrisc/trunk/orpsocv2/

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