OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 513

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
506 ORPSoC or1200 interrupt and syscall generation test julius 4792d 13h /openrisc/trunk/orpsocv2/
505 OR1200 overflow detection fixup

SPIflash program update

or1200 driver library timer improvement
julius 4792d 14h /openrisc/trunk/orpsocv2/
504 ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup julius 4809d 10h /openrisc/trunk/orpsocv2/
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4810d 06h /openrisc/trunk/orpsocv2/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default
julius 4812d 10h /openrisc/trunk/orpsocv2/
501 ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default
julius 4813d 10h /openrisc/trunk/orpsocv2/
500 ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc

ML501 simulation makefile update to allow custom ELFs to be specified
julius 4813d 13h /openrisc/trunk/orpsocv2/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4814d 06h /openrisc/trunk/orpsocv2/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4816d 17h /openrisc/trunk/orpsocv2/
495 ORPSoC adding more accessor functions to Micron SDRAM model. julius 4816d 17h /openrisc/trunk/orpsocv2/
493 ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. julius 4829d 19h /openrisc/trunk/orpsocv2/
492 ORPSoC VPI interface for modelsim and documentation update julius 4830d 17h /openrisc/trunk/orpsocv2/
491 ORPSoC or1200_monitor update. julius 4831d 04h /openrisc/trunk/orpsocv2/
489 ORPSoC sw cleanup. Remove warnings. julius 4840d 16h /openrisc/trunk/orpsocv2/
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4840d 17h /openrisc/trunk/orpsocv2/
487 ORPSoC main software makefile update julius 4843d 15h /openrisc/trunk/orpsocv2/
486 ORPSoC updates, mainly software, i2c driver julius 4843d 15h /openrisc/trunk/orpsocv2/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4847d 19h /openrisc/trunk/orpsocv2/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4865d 00h /openrisc/trunk/orpsocv2/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4865d 23h /openrisc/trunk/orpsocv2/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.