| Rev |
Log message |
Author |
Age |
Path |
| 500 |
ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc
ML501 simulation makefile update to allow custom ELFs to be specified |
julius |
4808d 13h |
/openrisc/trunk/orpsocv2/bench/ |
| 495 |
ORPSoC adding more accessor functions to Micron SDRAM model. |
julius |
4811d 17h |
/openrisc/trunk/orpsocv2/bench/ |
| 493 |
ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. |
julius |
4824d 19h |
/openrisc/trunk/orpsocv2/bench/ |
| 491 |
ORPSoC or1200_monitor update. |
julius |
4826d 04h |
/openrisc/trunk/orpsocv2/bench/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4842d 19h |
/openrisc/trunk/orpsocv2/bench/ |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4862d 23h |
/openrisc/trunk/orpsocv2/bench/ |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4868d 20h |
/openrisc/trunk/orpsocv2/bench/ |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4870d 22h |
/openrisc/trunk/orpsocv2/bench/ |
| 456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
4882d 15h |
/openrisc/trunk/orpsocv2/bench/ |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
4895d 10h |
/openrisc/trunk/orpsocv2/bench/ |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4902d 13h |
/openrisc/trunk/orpsocv2/bench/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4909d 05h |
/openrisc/trunk/orpsocv2/bench/ |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
4922d 05h |
/openrisc/trunk/orpsocv2/bench/ |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4930d 14h |
/openrisc/trunk/orpsocv2/bench/ |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
4936d 04h |
/openrisc/trunk/orpsocv2/bench/ |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4937d 09h |
/openrisc/trunk/orpsocv2/bench/ |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4939d 15h |
/openrisc/trunk/orpsocv2/bench/ |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
4987d 21h |
/openrisc/trunk/orpsocv2/bench/ |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
4989d 06h |
/openrisc/trunk/orpsocv2/bench/ |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
4989d 11h |
/openrisc/trunk/orpsocv2/bench/ |
