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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] - Rev 542

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Rev	Log message	Author	Age	Path
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5000d 13h	/openrisc/trunk/orpsocv2/bench/
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5002d 13h	/openrisc/trunk/orpsocv2/bench/
353	OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability. * or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: "" * or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: "" * or1200/rtl/verilog/or1200_except.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_except.v: "" * orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some Verilator related Lint issues fixed. ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and updated RAM model hooks for new RAM. * orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping * orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: "" * orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping, change include and classes for new RAM model. * orpsocv2/bench/sysc/src/OrpsocAccess.cpp: "" or_debug_proxy - fixing sleep and Windows make issues: * or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly * or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated) ORPmon play around, various changes to low level files.	julius	5002d 15h	/openrisc/trunk/orpsocv2/bench/
351	OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO	julius	5003d 13h	/openrisc/trunk/orpsocv2/bench/
348	First stage of ORPSoCv2 update - more to come	julius	5003d 17h	/openrisc/trunk/orpsocv2/bench/
70	ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\!	julius	5204d 02h	/openrisc/trunk/orpsocv2/bench/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5204d 03h	/openrisc/trunk/orpsocv2/bench/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5206d 22h	/openrisc/trunk/orpsocv2/bench/
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5226d 20h	/openrisc/trunk/orpsocv2/bench/
65	ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix	julius	5231d 02h	/openrisc/trunk/orpsocv2/bench/

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