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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] - Rev 864

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Rev Log message Author Age Path
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4923d 17h /openrisc/trunk/orpsocv2/bench/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4929d 07h /openrisc/trunk/orpsocv2/bench/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4930d 12h /openrisc/trunk/orpsocv2/bench/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4932d 18h /openrisc/trunk/orpsocv2/bench/
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 4981d 00h /openrisc/trunk/orpsocv2/bench/
362 ORPSoCv2 verilator building working again. Board build fixes to follow julius 4982d 09h /openrisc/trunk/orpsocv2/bench/
361 OPRSoCv2 - adding things left out in last check-in julius 4982d 14h /openrisc/trunk/orpsocv2/bench/
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 4982d 14h /openrisc/trunk/orpsocv2/bench/
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 4984d 14h /openrisc/trunk/orpsocv2/bench/
353 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.

ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""

or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)

ORPmon play around, various changes to low level files.		 julius 4984d 16h /openrisc/trunk/orpsocv2/bench/

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