| Rev |
Log message |
Author |
Age |
Path |
| 495 |
ORPSoC adding more accessor functions to Micron SDRAM model. |
julius |
4822d 22h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 493 |
ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. |
julius |
4836d 00h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 491 |
ORPSoC or1200_monitor update. |
julius |
4837d 08h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4854d 00h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4874d 04h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4880d 00h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
4893d 19h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
4906d 14h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4913d 18h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
4933d 10h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4941d 18h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
4947d 08h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4948d 14h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4950d 20h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5000d 15h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5000d 16h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5002d 15h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5003d 16h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5003d 20h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5204d 06h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
