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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Rev 49

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49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5363d 14h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
6 Checking in ORPSoCv2 julius 5477d 12h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v

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