URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.c] - Rev 397

Rev	Log message	Author	Age	Path
397	ORPSoCv2: doc/ path added, with Texinfo documentation. Still a work in progress. VPI files updated. OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction. Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.	julius	4948d 08h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5361d 01h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5376d 12h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5456d 12h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c