URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [verilog/] [vpi_debug_module.v] - Rev 49

Rev	Log message	Author	Age	Path
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5363d 14h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_module.v
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5379d 01h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_module.v
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5459d 01h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_module.v