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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] - Rev 866

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Rev Log message Author Age Path
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4794d 15h /openrisc/trunk/orpsocv2/boards/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default		 julius 4796d 19h /openrisc/trunk/orpsocv2/boards/
500 ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc

ML501 simulation makefile update to allow custom ELFs to be specified		 julius 4797d 23h /openrisc/trunk/orpsocv2/boards/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4798d 16h /openrisc/trunk/orpsocv2/boards/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4801d 02h /openrisc/trunk/orpsocv2/boards/
492 ORPSoC VPI interface for modelsim and documentation update julius 4815d 02h /openrisc/trunk/orpsocv2/boards/
486 ORPSoC updates, mainly software, i2c driver julius 4828d 00h /openrisc/trunk/orpsocv2/boards/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4832d 05h /openrisc/trunk/orpsocv2/boards/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4849d 09h /openrisc/trunk/orpsocv2/boards/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4850d 08h /openrisc/trunk/orpsocv2/boards/

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