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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] - Rev 652

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Rev Log message Author Age Path
652 Fix make compile.tcl for actel backend yannv 4591d 23h /openrisc/trunk/orpsocv2/boards/actel/
563 Search for external cores in <board>/modules path olof 4708d 15h /openrisc/trunk/orpsocv2/boards/actel/
544 ORPSoC ordb1a3pe1500 update - adding SD card controller. julius 4734d 03h /openrisc/trunk/orpsocv2/boards/actel/
542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.
julius 4739d 17h /openrisc/trunk/orpsocv2/boards/actel/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE
julius 4763d 03h /openrisc/trunk/orpsocv2/boards/actel/
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4806d 14h /openrisc/trunk/orpsocv2/boards/actel/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default
julius 4808d 18h /openrisc/trunk/orpsocv2/boards/actel/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4810d 14h /openrisc/trunk/orpsocv2/boards/actel/
492 ORPSoC VPI interface for modelsim and documentation update julius 4827d 01h /openrisc/trunk/orpsocv2/boards/actel/
486 ORPSoC updates, mainly software, i2c driver julius 4839d 22h /openrisc/trunk/orpsocv2/boards/actel/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4844d 03h /openrisc/trunk/orpsocv2/boards/actel/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4861d 07h /openrisc/trunk/orpsocv2/boards/actel/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4865d 02h /openrisc/trunk/orpsocv2/boards/actel/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI
julius 4870d 03h /openrisc/trunk/orpsocv2/boards/actel/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 4896d 17h /openrisc/trunk/orpsocv2/boards/actel/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 4903d 21h /openrisc/trunk/orpsocv2/boards/actel/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.
julius 4910d 12h /openrisc/trunk/orpsocv2/boards/actel/
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.
julius 4923d 13h /openrisc/trunk/orpsocv2/boards/actel/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 4931d 22h /openrisc/trunk/orpsocv2/boards/actel/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.
julius 4935d 23h /openrisc/trunk/orpsocv2/boards/actel/

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