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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [bench/] [verilog/] [include] - Rev 530

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Rev Log message Author Age Path
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4756d 05h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4896d 23h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4929d 01h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 4930d 01h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4930d 14h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include

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