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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [include/] [or1200_defines.v] - Rev 854

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Rev Log message Author Age Path
854 Add OR1200_OR32_LWS define to board specific or1200_defines.v stekern 4167d 23h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4755d 18h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4799d 05h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default		 julius 4801d 09h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4803d 06h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4903d 04h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4930d 03h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v

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