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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [syn/] [synplify/] [bin/] [Makefile] - Rev 449

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Rev Log message Author Age Path
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 5176d 04h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 5183d 08h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 5211d 08h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.
julius 5215d 10h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 5216d 22h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile

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