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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [syn/] [synplify] - Rev 542

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542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.		 julius 4732d 16h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4756d 02h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 4863d 02h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4889d 16h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4896d 20h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4924d 20h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4928d 22h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4930d 10h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify

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