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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] - Rev 563

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Rev Log message Author Age Path
563 Search for external cores in <board>/modules path olof 4708d 10h /openrisc/trunk/orpsocv2/boards/xilinx/
560 ORPSoC update - update make scripts, XILINX_PATH setup changes.

Note - may require a change to XILINX_PATH on user systems.
julius 4716d 08h /openrisc/trunk/orpsocv2/boards/xilinx/
542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.
julius 4739d 11h /openrisc/trunk/orpsocv2/boards/xilinx/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE
julius 4762d 21h /openrisc/trunk/orpsocv2/boards/xilinx/
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4806d 08h /openrisc/trunk/orpsocv2/boards/xilinx/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default
julius 4808d 12h /openrisc/trunk/orpsocv2/boards/xilinx/
500 ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc

ML501 simulation makefile update to allow custom ELFs to be specified
julius 4809d 16h /openrisc/trunk/orpsocv2/boards/xilinx/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4810d 09h /openrisc/trunk/orpsocv2/boards/xilinx/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4812d 19h /openrisc/trunk/orpsocv2/boards/xilinx/
492 ORPSoC VPI interface for modelsim and documentation update julius 4826d 19h /openrisc/trunk/orpsocv2/boards/xilinx/
486 ORPSoC updates, mainly software, i2c driver julius 4839d 17h /openrisc/trunk/orpsocv2/boards/xilinx/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4843d 21h /openrisc/trunk/orpsocv2/boards/xilinx/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4861d 02h /openrisc/trunk/orpsocv2/boards/xilinx/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4862d 01h /openrisc/trunk/orpsocv2/boards/xilinx/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4863d 17h /openrisc/trunk/orpsocv2/boards/xilinx/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4864d 21h /openrisc/trunk/orpsocv2/boards/xilinx/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI
julius 4869d 22h /openrisc/trunk/orpsocv2/boards/xilinx/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 4896d 12h /openrisc/trunk/orpsocv2/boards/xilinx/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 4903d 16h /openrisc/trunk/orpsocv2/boards/xilinx/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.
julius 4910d 07h /openrisc/trunk/orpsocv2/boards/xilinx/

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