OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] - Rev 866

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
500 ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc

ML501 simulation makefile update to allow custom ELFs to be specified		 julius 4811d 04h /openrisc/trunk/orpsocv2/boards/xilinx/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4811d 21h /openrisc/trunk/orpsocv2/boards/xilinx/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4814d 07h /openrisc/trunk/orpsocv2/boards/xilinx/
492 ORPSoC VPI interface for modelsim and documentation update julius 4828d 08h /openrisc/trunk/orpsocv2/boards/xilinx/
486 ORPSoC updates, mainly software, i2c driver julius 4841d 05h /openrisc/trunk/orpsocv2/boards/xilinx/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4845d 10h /openrisc/trunk/orpsocv2/boards/xilinx/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4862d 14h /openrisc/trunk/orpsocv2/boards/xilinx/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4863d 14h /openrisc/trunk/orpsocv2/boards/xilinx/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4865d 05h /openrisc/trunk/orpsocv2/boards/xilinx/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4866d 09h /openrisc/trunk/orpsocv2/boards/xilinx/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.