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866 orpsocv2: correct build/par issue on Atlys board

From patch submission e-mail:

The first of the series is an issue that has been around since the
beginning (at least based on the svn log files) and traces its root to the
first Xilinx board supported by orpsocv2, the ML501. Apparently Makefile
for the final place-and-route process in all the builds contains a typo
which leads to the routing tool not using any timing constraint at all.

Patch by: Jason Zheng <jxzheng@gmail.com>
stekern 3659d 02h /openrisc/trunk/orpsocv2/boards/xilinx/atlys/
854 Add OR1200_OR32_LWS define to board specific or1200_defines.v stekern 4163d 03h /openrisc/trunk/orpsocv2/boards/xilinx/atlys/
677 atlys: add 2-clock synchronizer chain for ddr2_calib_done

The signal ddr2_calib_done signal comes from the ddr2 clock domain,
while wb_req is treating it as if it came from wb_clk domain. As a
result the timing analysis tool assumed a worst case scenario of 5ns
between the two domains and the results were miserable.

While we can argue that this is a multi-cycle path, the fact is that
ddr2_calib_done feeds into multiple logic sinks and can potentially
cause meta-stability issue in the design. The solution is to add a
2-clock meta-stability filter to address both the timing problems and
the meta-stability concern.

Signed-off-by: Jason Zheng <jxzheng@gmail.com>
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Acked-by: Olof Kindgren <olof.kindgren@orsoc.se>
stekern 4449d 16h /openrisc/trunk/orpsocv2/boards/xilinx/atlys/
638 orpsoc: xilinx: use XILINX env variable

instead of rely on custom environment variables,
use the XILINX variable and instruct the user how to
source the scripts that set it.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4626d 04h /openrisc/trunk/orpsocv2/boards/xilinx/atlys/
634 orpsoc: atlys: autoregenerate coregen cores

Instead of keeping binary .ngc files of the coregen
generated cores, use coregen to generate them from the .xco
and .cgp file
stekern 4631d 04h /openrisc/trunk/orpsocv2/boards/xilinx/atlys/
633 orpsoc: add Digilent Atlys spartan6 board README

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4631d 04h /openrisc/trunk/orpsocv2/boards/xilinx/atlys/
632 orpsoc: add Digilent Atlys spartan6 board sw include file

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4631d 04h /openrisc/trunk/orpsocv2/boards/xilinx/atlys/
631 orpsoc: add Digilent Atlys spartan6 board testbench

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4631d 04h /openrisc/trunk/orpsocv2/boards/xilinx/atlys/
630 orpsoc: add Digilent Atlys spartan6 board backend

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4631d 04h /openrisc/trunk/orpsocv2/boards/xilinx/atlys/
629 orpsoc: add Digilent Atlys spartan6 board or1ksim configuration

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4631d 04h /openrisc/trunk/orpsocv2/boards/xilinx/atlys/
628 orpsoc: add Digilent Atlys spartan6 board Makefiles

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4631d 04h /openrisc/trunk/orpsocv2/boards/xilinx/atlys/
627 orpsoc: add Digilent Atlys spartan6 board rtl

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4631d 04h /openrisc/trunk/orpsocv2/boards/xilinx/atlys/

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