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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] - Rev 854

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Rev Log message Author Age Path
854 Add OR1200_OR32_LWS define to board specific or1200_defines.v stekern 4163d 11h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4571d 18h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
638 orpsoc: xilinx: use XILINX env variable

instead of rely on custom environment variables,
use the XILINX variable and instruct the user how to
source the scripts that set it.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4626d 12h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
563 Search for external cores in <board>/modules path olof 4696d 18h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
560 ORPSoC update - update make scripts, XILINX_PATH setup changes.

Note - may require a change to XILINX_PATH on user systems.
julius 4704d 16h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.
julius 4727d 19h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE
julius 4751d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4794d 16h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default
julius 4796d 20h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
500 ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc

ML501 simulation makefile update to allow custom ELFs to be specified
julius 4798d 00h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4798d 17h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4801d 03h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
492 ORPSoC VPI interface for modelsim and documentation update julius 4815d 03h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
486 ORPSoC updates, mainly software, i2c driver julius 4828d 01h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4832d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4849d 10h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4850d 09h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4852d 01h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4853d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI
julius 4858d 06h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/

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