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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [backend/] [par/] - Rev 655

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Rev Log message Author Age Path
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4586d 08h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
638 orpsoc: xilinx: use XILINX env variable

instead of rely on custom environment variables,
use the XILINX variable and instruct the user how to
source the scripts that set it.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4641d 01h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
560 ORPSoC update - update make scripts, XILINX_PATH setup changes.

Note - may require a change to XILINX_PATH on user systems.		 julius 4719d 06h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.		 julius 4742d 09h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4765d 19h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4815d 17h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4864d 23h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4866d 14h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4899d 09h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4934d 14h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5197d 01h /par/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5199d 20h /par/

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