OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] - Rev 655

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4570d 17h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4750d 04h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4831d 04h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4848d 08h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4890d 22h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4918d 23h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4922d 12h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 4977d 20h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.