OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] - Rev 854

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
854 Add OR1200_OR32_LWS define to board specific or1200_defines.v stekern 4163d 01h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4571d 09h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4750d 20h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4794d 07h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default		 julius 4796d 11h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4798d 07h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4800d 18h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4831d 20h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4849d 00h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4850d 00h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4851d 15h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4891d 14h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4898d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 4911d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4919d 15h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4923d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5182d 02h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5184d 21h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.