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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [syn/] - Rev 655

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Rev Log message Author Age Path
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4570d 21h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/
638 orpsoc: xilinx: use XILINX env variable

instead of rely on custom environment variables,
use the XILINX variable and instruct the user how to
source the scripts that set it.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4625d 14h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/
542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.		 julius 4726d 22h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4750d 08h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 4857d 08h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4883d 22h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4891d 02h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4897d 17h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4919d 02h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5181d 14h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5184d 08h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/

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