OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [doc/] [orpsoc.texi] - Rev 655

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4577d 22h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
650 ORPSoC: documentation update to fix explanation of Xilinx environment setup, add section for Atlys board, various cleanups julius 4591d 22h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
568 OPRSoC - adding Xilinx Xtreme DSP Spartan-3A 1800A board port and documentation julius 4690d 08h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
564 Update docs for new modules sub directory olof 4702d 21h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
560 ORPSoC update - update make scripts, XILINX_PATH setup changes.

Note - may require a change to XILINX_PATH on user systems.
julius 4710d 20h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.
julius 4733d 23h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE
julius 4757d 09h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4807d 07h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
492 ORPSoC VPI interface for modelsim and documentation update julius 4821d 07h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4838d 09h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4856d 13h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI
julius 4864d 10h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 4891d 00h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 4898d 03h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.
julius 4917d 19h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 4926d 04h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
410 ORPSoC: Adding README in root explaining how to build documentation, and
documentation fixup so it builds properly again.
julius 4931d 05h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.
julius 4931d 05h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4931d 18h /openrisc/trunk/orpsocv2/doc/orpsoc.texi
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.
julius 4935d 05h /openrisc/trunk/orpsocv2/doc/orpsoc.texi

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.