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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] - Rev 867

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853 Declare pcreg_boot before usage

When things were moved around in rev 813, this error was introduced

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>
olof 4410d 21h /openrisc/trunk/orpsocv2/rtl/
850 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>
stekern 4425d 13h /openrisc/trunk/orpsocv2/rtl/
849 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>
stekern 4425d 13h /openrisc/trunk/orpsocv2/rtl/
848 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>
stekern 4425d 13h /openrisc/trunk/orpsocv2/rtl/
815 OR1200 debug unit: prevent deadlock when trap instruction stalls

As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.

The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result.
yannv 4446d 07h /openrisc/trunk/orpsocv2/rtl/
814 orpsoc/or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
olof 4460d 23h /openrisc/trunk/orpsocv2/rtl/
807 ORPSoC: Commit for bug 85 - add DSX support to OR1200.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85

Also added software tests, and added these tests to default regression test list
julius 4576d 17h /openrisc/trunk/orpsocv2/rtl/
805 ORPSoC: Fix for bug 90 - EPCR on range exception bug

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90
julius 4576d 17h /openrisc/trunk/orpsocv2/rtl/
803 ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91
julius 4576d 17h /openrisc/trunk/orpsocv2/rtl/
801 ORPSoC: Fix bug 88

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88
julius 4581d 23h /openrisc/trunk/orpsocv2/rtl/
794 ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file

Fixes lint warnings.
julius 4615d 08h /openrisc/trunk/orpsocv2/rtl/
788 or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
julius 4639d 22h /openrisc/trunk/orpsocv2/rtl/
679 Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
olof 4663d 22h /openrisc/trunk/orpsocv2/rtl/
672 ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled

OR1200 RTL fix and software test added.
julius 4742d 18h /openrisc/trunk/orpsocv2/rtl/
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4793d 20h /openrisc/trunk/orpsocv2/rtl/
619 ORPSoC OR1200 fix and regression test for bug 51.

signed-off Julius Baxter
reviewed by Stefan Kristiansson
julius 4874d 19h /openrisc/trunk/orpsocv2/rtl/
618 Remove unused parameter Tp olof 4875d 03h /openrisc/trunk/orpsocv2/rtl/
570 Fix white space in ethmac headers olof 4889d 22h /openrisc/trunk/orpsocv2/rtl/
547 ORPSoC dbg_if fix for slow Wishbone slaves julius 4937d 05h /openrisc/trunk/orpsocv2/rtl/
546 ORPSoC update: Fix WB B3 bursting termination on error in WB B3 RAM model julius 4937d 22h /openrisc/trunk/orpsocv2/rtl/

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