| Rev |
Log message |
Author |
Age |
Path |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4872d 10h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4879d 16h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
4891d 09h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4911d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4917d 23h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
4930d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4939d 08h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
4942d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
4943d 10h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
4944d 10h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
4944d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4946d 03h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4948d 09h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 392 |
ORPSoCv2 software path reorganisation stage 1. |
julius |
4952d 00h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 391 |
Removing modules no longer needed in ORPSoCv2 |
julius |
4953d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 373 |
ORPSoCv2 software update for compatibility with OR toolchain 1.0 |
julius |
4984d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 364 |
OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.
OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)
OR1200 spec updated to version 0.9, various updates.
OR1200 in ORPSoC and main OR1200 in sync, only difference is defines. |
julius |
4996d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
4996d 15h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
4998d 00h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
4998d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
