| Rev |
Log message |
Author |
Age |
Path |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4817d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4851d 11h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4869d 15h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4871d 06h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4871d 15h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4872d 08h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4879d 14h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
4891d 06h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4911d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4917d 20h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
4930d 20h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4939d 06h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
4942d 19h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
4943d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
4944d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
4944d 19h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4946d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4948d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 392 |
ORPSoCv2 software path reorganisation stage 1. |
julius |
4951d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 391 |
Removing modules no longer needed in ORPSoCv2 |
julius |
4952d 23h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
