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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] - Rev 848

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848 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>
stekern 4222d 19h /openrisc/trunk/orpsocv2/rtl/verilog/
815 OR1200 debug unit: prevent deadlock when trap instruction stalls

As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.

The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result.
yannv 4243d 13h /openrisc/trunk/orpsocv2/rtl/verilog/
814 orpsoc/or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
olof 4258d 06h /openrisc/trunk/orpsocv2/rtl/verilog/
807 ORPSoC: Commit for bug 85 - add DSX support to OR1200.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85

Also added software tests, and added these tests to default regression test list
julius 4373d 23h /openrisc/trunk/orpsocv2/rtl/verilog/
805 ORPSoC: Fix for bug 90 - EPCR on range exception bug

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90
julius 4374d 00h /openrisc/trunk/orpsocv2/rtl/verilog/
803 ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91
julius 4374d 00h /openrisc/trunk/orpsocv2/rtl/verilog/
801 ORPSoC: Fix bug 88

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88
julius 4379d 05h /openrisc/trunk/orpsocv2/rtl/verilog/
794 ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file

Fixes lint warnings.
julius 4412d 15h /openrisc/trunk/orpsocv2/rtl/verilog/
788 or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
julius 4437d 05h /openrisc/trunk/orpsocv2/rtl/verilog/
679 Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
olof 4461d 05h /openrisc/trunk/orpsocv2/rtl/verilog/
672 ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled

OR1200 RTL fix and software test added.
julius 4540d 00h /openrisc/trunk/orpsocv2/rtl/verilog/
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4591d 02h /openrisc/trunk/orpsocv2/rtl/verilog/
619 ORPSoC OR1200 fix and regression test for bug 51.

signed-off Julius Baxter
reviewed by Stefan Kristiansson
julius 4672d 02h /openrisc/trunk/orpsocv2/rtl/verilog/
618 Remove unused parameter Tp olof 4672d 09h /openrisc/trunk/orpsocv2/rtl/verilog/
570 Fix white space in ethmac headers olof 4687d 05h /openrisc/trunk/orpsocv2/rtl/verilog/
547 ORPSoC dbg_if fix for slow Wishbone slaves julius 4734d 11h /openrisc/trunk/orpsocv2/rtl/verilog/
546 ORPSoC update: Fix WB B3 bursting termination on error in WB B3 RAM model julius 4735d 04h /openrisc/trunk/orpsocv2/rtl/verilog/
545 ORPSoC - revert unecessary i2c fix - driver oneliner was all that was needed. julius 4741d 06h /openrisc/trunk/orpsocv2/rtl/verilog/
543 i2c_master_slave bug fix for slave, potentially holding SDA low when master wants to send stop. julius 4741d 14h /openrisc/trunk/orpsocv2/rtl/verilog/
537 ORPSoC or1200 fix for l.rfe bug, and when multiply is disabled. julius 4758d 01h /openrisc/trunk/orpsocv2/rtl/verilog/

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