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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] - Rev 435

Rev	Log message	Author	Age	Path
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	4944d 08h	/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	4944d 21h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	4946d 02h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	4998d 04h	/openrisc/trunk/orpsocv2/rtl/verilog/eth/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5201d 18h	/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5299d 01h	/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/
6	Checking in ORPSoCv2	julius	5475d 00h	/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/