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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_wishbone.v] - Rev 570

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Rev Log message Author Age Path
570 Fix white space in ethmac headers olof 4667d 21h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4751d 05h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4832d 05h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4891d 23h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 4925d 02h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4926d 19h /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_wishbone.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 4978d 21h /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_wishbone.v
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5182d 11h /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_wishbone.v
6 Checking in ORPSoCv2 julius 5455d 17h /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_wishbone.v

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