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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] - Rev 439

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439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4915d 03h /openrisc/trunk/orpsocv2/rtl/verilog/include/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4921d 18h /openrisc/trunk/orpsocv2/rtl/verilog/include/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4943d 03h /openrisc/trunk/orpsocv2/rtl/verilog/include/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 4948d 05h /openrisc/trunk/orpsocv2/rtl/verilog/include/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4948d 17h /openrisc/trunk/orpsocv2/rtl/verilog/include/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4949d 23h /openrisc/trunk/orpsocv2/rtl/verilog/include/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4952d 04h /openrisc/trunk/orpsocv2/rtl/verilog/include/
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 4988d 03h /openrisc/trunk/orpsocv2/rtl/verilog/include/
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5000d 10h /openrisc/trunk/orpsocv2/rtl/verilog/include/
361 OPRSoCv2 - adding things left out in last check-in julius 5002d 00h /openrisc/trunk/orpsocv2/rtl/verilog/include/
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5002d 00h /openrisc/trunk/orpsocv2/rtl/verilog/include/

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