URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] [dbg_cpu_defines.v] - Rev 373

Rev	Log message	Author	Age	Path
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	4996d 15h	/openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	4998d 05h	/openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v
6	Checking in ORPSoCv2	julius	5475d 01h	/dbg_cpu_defines.v