URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] [orpsoc-defines.v] - Rev 503

Rev	Log message	Author	Age	Path
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	4939d 06h	/openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	4946d 01h	/openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
397	ORPSoCv2: doc/ path added, with Texinfo documentation. Still a work in progress. VPI files updated. OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction. Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.	julius	4948d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	4996d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
361	OPRSoCv2 - adding things left out in last check-in	julius	4998d 02h	/openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v