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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [jtag_tap/] - Rev 360

Rev	Log message	Author	Age	Path
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5001d 19h	/openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5208d 04h	/openrisc/trunk/orpsocv2/rtl/verilog/components/tap/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5302d 17h	/openrisc/trunk/orpsocv2/rtl/verilog/components/tap/
6	Checking in ORPSoCv2	julius	5478d 15h	/openrisc/trunk/orpsocv2/rtl/verilog/components/tap/