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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [jtag_tap/] - Rev 570

Rev	Log message	Author	Age	Path
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	4998d 14h	/openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/
361	OPRSoCv2 - adding things left out in last check-in	julius	5000d 04h	/openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5000d 04h	/openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5206d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/components/tap/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5301d 02h	/openrisc/trunk/orpsocv2/rtl/verilog/components/tap/
6	Checking in ORPSoCv2	julius	5477d 01h	/openrisc/trunk/orpsocv2/rtl/verilog/components/tap/