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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_genpc.v] - Rev 850

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850 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4203d 15h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v
814 orpsoc/or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4239d 01h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 4977d 10h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 4979d 00h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 4979d 09h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_genpc.v
350 Adding new OR1200 processor to ORPSoCv2 julius 4982d 04h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_genpc.v

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