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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [orpsoc_top/] - Rev 476

Rev	Log message	Author	Age	Path
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	4911d 05h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	4939d 06h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	4946d 01h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	4996d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	4998d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/