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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ram_wb/] [ram_wb_b3.v] - Rev 655

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Rev Log message Author Age Path
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4577d 03h /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
546 ORPSoC update: Fix WB B3 bursting termination on error in WB B3 RAM model julius 4721d 05h /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 4865d 17h /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4897d 08h /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4928d 23h /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 4984d 06h /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_sc_sw.v
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5328d 09h /openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb/ram_wb_sc_sw.v
6 Checking in ORPSoCv2 julius 5461d 02h /openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb/ram_wb_sc_sw.v

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