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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] - Rev 363

Rev	Log message	Author	Age	Path
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5000d 06h	/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/
361	OPRSoCv2 - adding things left out in last check-in	julius	5001d 20h	/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5001d 21h	/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5302d 18h	/openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5416d 05h	/openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/
6	Checking in ORPSoCv2	julius	5478d 17h	/openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/