OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] - Rev 632

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 5002d 20h /openrisc/trunk/orpsocv2/sim/
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5003d 20h /openrisc/trunk/orpsocv2/sim/
348 First stage of ORPSoCv2 update - more to come julius 5004d 01h /openrisc/trunk/orpsocv2/sim/
78 Fixed typo in Silos workaround script rherveille 5156d 20h /openrisc/trunk/orpsocv2/sim/
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5156d 20h /openrisc/trunk/orpsocv2/sim/
76 Added: +libext+.v
Added: +incdir+.		 rherveille 5157d 19h /openrisc/trunk/orpsocv2/sim/
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5204d 10h /openrisc/trunk/orpsocv2/sim/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5204d 11h /openrisc/trunk/orpsocv2/sim/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5207d 02h /openrisc/trunk/orpsocv2/sim/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5207d 05h /openrisc/trunk/orpsocv2/sim/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.