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[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] - Rev 807

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Rev Log message Author Age Path
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 4991d 06h /openrisc/trunk/orpsocv2/sim/bin/
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 4992d 11h /openrisc/trunk/orpsocv2/sim/bin/
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 4993d 12h /openrisc/trunk/orpsocv2/sim/bin/
348 First stage of ORPSoCv2 update - more to come julius 4993d 16h /openrisc/trunk/orpsocv2/sim/bin/
78 Fixed typo in Silos workaround script rherveille 5146d 11h /openrisc/trunk/orpsocv2/sim/bin/
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5146d 11h /openrisc/trunk/orpsocv2/sim/bin/
76 Added: +libext+.v
Added: +incdir+.		 rherveille 5147d 11h /openrisc/trunk/orpsocv2/sim/bin/
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5194d 01h /openrisc/trunk/orpsocv2/sim/bin/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5194d 02h /openrisc/trunk/orpsocv2/sim/bin/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5196d 18h /openrisc/trunk/orpsocv2/sim/bin/

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