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[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Rev 468

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468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 4876d 23h /openrisc/trunk/orpsocv2/sim/bin/Makefile
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4903d 13h /openrisc/trunk/orpsocv2/sim/bin/Makefile
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4917d 08h /openrisc/trunk/orpsocv2/sim/bin/Makefile
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.		 julius 4923d 15h /openrisc/trunk/orpsocv2/sim/bin/Makefile
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 4930d 08h /openrisc/trunk/orpsocv2/sim/bin/Makefile
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4945d 12h /openrisc/trunk/orpsocv2/sim/bin/Makefile
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4947d 18h /openrisc/trunk/orpsocv2/sim/bin/Makefile
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 4950d 17h /openrisc/trunk/orpsocv2/sim/bin/Makefile
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 4996d 00h /openrisc/trunk/orpsocv2/sim/bin/Makefile
362 ORPSoCv2 verilator building working again. Board build fixes to follow julius 4997d 09h /openrisc/trunk/orpsocv2/sim/bin/Makefile
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 4997d 14h /openrisc/trunk/orpsocv2/sim/bin/Makefile
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 4998d 08h /openrisc/trunk/orpsocv2/sim/bin/Makefile
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 4999d 14h /openrisc/trunk/orpsocv2/sim/bin/Makefile
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5000d 14h /openrisc/trunk/orpsocv2/sim/bin/Makefile
348 First stage of ORPSoCv2 update - more to come julius 5000d 18h /openrisc/trunk/orpsocv2/sim/bin/Makefile
78 Fixed typo in Silos workaround script rherveille 5153d 13h /openrisc/trunk/orpsocv2/sim/bin/Makefile
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5153d 14h /openrisc/trunk/orpsocv2/sim/bin/Makefile
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5201d 03h /openrisc/trunk/orpsocv2/sim/bin/Makefile
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5201d 04h /openrisc/trunk/orpsocv2/sim/bin/Makefile
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5203d 20h /openrisc/trunk/orpsocv2/sim/bin/Makefile

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