URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Rev 49

Rev	Log message	Author	Age	Path
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5363d 14h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5415d 01h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5438d 22h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5454d 19h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5459d 01h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
36	Better clean rule in makefile	julius	5473d 02h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
6	Checking in ORPSoCv2	julius	5477d 13h	/openrisc/trunk/orpsocv2/sim/bin/Makefile