| Rev |
Log message |
Author |
Age |
Path |
| 412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
4945d 02h |
/openrisc/trunk/orpsocv2/sw/ |
| 411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
4945d 14h |
/openrisc/trunk/orpsocv2/sw/ |
| 409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
4946d 13h |
/openrisc/trunk/orpsocv2/sw/ |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
4947d 02h |
/openrisc/trunk/orpsocv2/sw/ |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4948d 07h |
/openrisc/trunk/orpsocv2/sw/ |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4950d 13h |
/openrisc/trunk/orpsocv2/sw/ |
| 396 |
ORPSoCv2 final software fixes...for now. See updated README |
julius |
4953d 12h |
/openrisc/trunk/orpsocv2/sw/ |
| 395 |
ORPSoCv2 moving ethernet tests to correct place |
julius |
4953d 12h |
/openrisc/trunk/orpsocv2/sw/ |
| 394 |
ORPSoCv2 removing unused directories |
julius |
4953d 12h |
/openrisc/trunk/orpsocv2/sw/ |
| 393 |
ORPSoCv2 software rearrangement in progress. Basic tests should now run again. |
julius |
4953d 12h |
/openrisc/trunk/orpsocv2/sw/ |
| 392 |
ORPSoCv2 software path reorganisation stage 1. |
julius |
4954d 04h |
/openrisc/trunk/orpsocv2/sw/ |
| 374 |
ORPSoCv2 adding some files forgotten from last checkin |
julius |
4986d 11h |
/openrisc/trunk/orpsocv2/sw/ |
| 373 |
ORPSoCv2 software update for compatibility with OR toolchain 1.0 |
julius |
4986d 11h |
/openrisc/trunk/orpsocv2/sw/ |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
4998d 19h |
/openrisc/trunk/orpsocv2/sw/ |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5000d 09h |
/openrisc/trunk/orpsocv2/sw/ |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5000d 09h |
/openrisc/trunk/orpsocv2/sw/ |
| 358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5000d 18h |
/openrisc/trunk/orpsocv2/sw/ |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5001d 03h |
/openrisc/trunk/orpsocv2/sw/ |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5002d 09h |
/openrisc/trunk/orpsocv2/sw/ |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5003d 09h |
/openrisc/trunk/orpsocv2/sw/ |
| 349 |
ORPSoCv2 update with new software and makefile update |
julius |
5003d 13h |
/openrisc/trunk/orpsocv2/sw/ |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5003d 13h |
/openrisc/trunk/orpsocv2/sw/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5206d 18h |
/openrisc/trunk/orpsocv2/sw/ |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5226d 16h |
/openrisc/trunk/orpsocv2/sw/ |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5243d 14h |
/openrisc/trunk/orpsocv2/sw/ |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5285d 10h |
/openrisc/trunk/orpsocv2/sw/ |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5344d 12h |
/openrisc/trunk/orpsocv2/sw/ |
| 50 |
Adding or32_funcs.S |
julius |
5344d 17h |
/openrisc/trunk/orpsocv2/sw/ |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5363d 06h |
/openrisc/trunk/orpsocv2/sw/ |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5378d 18h |
/openrisc/trunk/orpsocv2/sw/ |
