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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] - Rev 439

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439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4915d 05h /openrisc/trunk/orpsocv2/sw/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4921d 20h /openrisc/trunk/orpsocv2/sw/
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.		 julius 4928d 04h /openrisc/trunk/orpsocv2/sw/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 4934d 19h /openrisc/trunk/orpsocv2/sw/
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 4934d 20h /openrisc/trunk/orpsocv2/sw/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4943d 05h /openrisc/trunk/orpsocv2/sw/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4946d 19h /openrisc/trunk/orpsocv2/sw/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4947d 07h /openrisc/trunk/orpsocv2/sw/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 4948d 07h /openrisc/trunk/orpsocv2/sw/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4948d 19h /openrisc/trunk/orpsocv2/sw/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4950d 01h /openrisc/trunk/orpsocv2/sw/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4952d 06h /openrisc/trunk/orpsocv2/sw/
396 ORPSoCv2 final software fixes...for now. See updated README julius 4955d 05h /openrisc/trunk/orpsocv2/sw/
395 ORPSoCv2 moving ethernet tests to correct place julius 4955d 06h /openrisc/trunk/orpsocv2/sw/
394 ORPSoCv2 removing unused directories julius 4955d 06h /openrisc/trunk/orpsocv2/sw/
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 4955d 06h /openrisc/trunk/orpsocv2/sw/
392 ORPSoCv2 software path reorganisation stage 1. julius 4955d 22h /openrisc/trunk/orpsocv2/sw/
374 ORPSoCv2 adding some files forgotten from last checkin julius 4988d 05h /openrisc/trunk/orpsocv2/sw/
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 4988d 05h /openrisc/trunk/orpsocv2/sw/
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5000d 12h /openrisc/trunk/orpsocv2/sw/

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