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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] - Rev 499

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Rev Log message Author Age Path
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4818d 00h /openrisc/trunk/orpsocv2/sw/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4820d 11h /openrisc/trunk/orpsocv2/sw/
489 ORPSoC sw cleanup. Remove warnings. julius 4844d 10h /openrisc/trunk/orpsocv2/sw/
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4844d 11h /openrisc/trunk/orpsocv2/sw/
487 ORPSoC main software makefile update julius 4847d 08h /openrisc/trunk/orpsocv2/sw/
486 ORPSoC updates, mainly software, i2c driver julius 4847d 08h /openrisc/trunk/orpsocv2/sw/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4851d 13h /openrisc/trunk/orpsocv2/sw/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4869d 17h /openrisc/trunk/orpsocv2/sw/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.
julius 4871d 17h /openrisc/trunk/orpsocv2/sw/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4872d 12h /openrisc/trunk/orpsocv2/sw/
470 ORPSoC OR1200 crt0 updates. julius 4876d 12h /openrisc/trunk/orpsocv2/sw/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI
julius 4877d 14h /openrisc/trunk/orpsocv2/sw/
466 ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README
julius 4878d 17h /openrisc/trunk/orpsocv2/sw/
465 ORPSoC SPI flash load Makefile and README updates. julius 4879d 07h /openrisc/trunk/orpsocv2/sw/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.
julius 4879d 16h /openrisc/trunk/orpsocv2/sw/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 4904d 03h /openrisc/trunk/orpsocv2/sw/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 4911d 07h /openrisc/trunk/orpsocv2/sw/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.
julius 4917d 22h /openrisc/trunk/orpsocv2/sw/
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.
julius 4924d 06h /openrisc/trunk/orpsocv2/sw/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...
julius 4930d 22h /openrisc/trunk/orpsocv2/sw/

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