OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] - Rev 628

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
619 ORPSoC OR1200 fix and regression test for bug 51.

signed-off Julius Baxter
reviewed by Stefan Kristiansson
julius 4664d 20h /openrisc/trunk/orpsocv2/sw/
567 ORPSoC ethmac test and diagnosis software program updates. julius 4696d 10h /openrisc/trunk/orpsocv2/sw/
545 ORPSoC - revert unecessary i2c fix - driver oneliner was all that was needed. julius 4734d 01h /openrisc/trunk/orpsocv2/sw/
542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.
julius 4739d 21h /openrisc/trunk/orpsocv2/sw/
535 ORPSoC - adding sw tests for l.rfe julius 4755d 23h /openrisc/trunk/orpsocv2/sw/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE
julius 4763d 08h /openrisc/trunk/orpsocv2/sw/
528 ORPSoC SPI flash programming link script bug fix julius 4768d 07h /openrisc/trunk/orpsocv2/sw/
506 ORPSoC or1200 interrupt and syscall generation test julius 4789d 02h /openrisc/trunk/orpsocv2/sw/
505 OR1200 overflow detection fixup

SPIflash program update

or1200 driver library timer improvement
julius 4789d 02h /openrisc/trunk/orpsocv2/sw/
504 ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup julius 4805d 22h /openrisc/trunk/orpsocv2/sw/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default
julius 4808d 22h /openrisc/trunk/orpsocv2/sw/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4810d 19h /openrisc/trunk/orpsocv2/sw/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4813d 05h /openrisc/trunk/orpsocv2/sw/
489 ORPSoC sw cleanup. Remove warnings. julius 4837d 05h /openrisc/trunk/orpsocv2/sw/
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4837d 05h /openrisc/trunk/orpsocv2/sw/
487 ORPSoC main software makefile update julius 4840d 03h /openrisc/trunk/orpsocv2/sw/
486 ORPSoC updates, mainly software, i2c driver julius 4840d 03h /openrisc/trunk/orpsocv2/sw/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4844d 08h /openrisc/trunk/orpsocv2/sw/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4862d 11h /openrisc/trunk/orpsocv2/sw/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.
julius 4864d 11h /openrisc/trunk/orpsocv2/sw/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.